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1 3mhz dual step-down converters and dual low-input ldos with i 2 c compatible interface isl9305 the isl9305 is an integrated mini power management ic (mini-pmic) ideal for applications of powering low-voltage microprocessor or multiple voltage rails with battery as input sources, such as a single li-ion or li-polymer. isl9305 integrates two high-efficiency 3mhz synchronous step-down converters (dcd1 and dcd2) and two low-input, low-dropout linear regulators (ldo1 and ldo2). the 3mhz pwm switching frequency allows the use of very small external inductors and capacitors. both step-down converters can enter skip mode under light load conditions to further improve the efficiency and maximize the battery life. for noise sensitive applications, they can also be programmed through i 2 c interface to operate in forced pwm mode regardless of the load current condition. the i 2 c interface supports on-the-fly slew rate control of the output voltage from 0.825v to 3.6v at 25mv/step size for dynamic power saving. each step-down converter can supply up to 800ma load current. the default output voltage can be set from 0.8v to v in using external feedback resistors on the adjustable version, or the isl9305 can be ordered in factory pre-set power-up default voltages in increments of 100mv from 0.9v to 3.6v. the isl9305 also provides two 300ma low dropout (ldo) regulators. the input voltage range is 1.5v to 5.5v allowing them to be powered from one of the on-chip step-down converters or directly from the battery. the default ldo power-up output comes with factory pre-set fixed output voltage options betw een 0.9v to 3.3v. the isl9305 is available in a 4mmx4mm 16 ld tqfn package. related literature ? fn7724 , isl9305h data sheet ? an1564 ?isl9305irtzeval1z an d isl9305hirtzeval1z evaluation boards? features ? dual 800ma, synchronous step-down converters and dual 300ma, general-purpose ldos ? input voltage range - dcd1/dcd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 5.5v - ldo1/ldo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to 5.5v ? 400kb/s i 2 c-bus series interface transfers the control data between the host controller and the isl9305 ? adjustable output voltage - dcd1/dcd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8v to v in -fixed output i 2 c programmability ? at 25mv/step . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.825v to 3.6v ?ldo1/ldo2 output voltage i 2 c programmability - at 50mv/step. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9v to 3.3v ?50 a i q (typ) with dcd1/dcd2 in skip mode; 20 a i q (typ) for each enabled ldo ?on-the-fly i 2 c programming of dc/dc and ldo output voltages ?dcd1/dcd2 i 2 c programmable skip mode under light load or forced fixed switching frequency pwm mode ? small, thin, 4mmx4mm tqfn package applications ? cellular phones, smart phones ? pdas, portable media players, portable instruments ? single li-ion/li-polymer battery-powered equipment ?dsp core power figure 1. typical application diagram * * isl9305 sdat vindcd1 vinldo1 vinldo2 l 1 = 1.5h sw1 fb1 sw2 fb2 voldo2 2.3v to 5.5v 800ma l 2 = 1.5h 800ma 1.5v to 5.5v 1.5v to 5.5v gnddcd1 300ma 300ma c 3 r 1 r 2 r 3 r 4 gnddcd2 sclk voldo1 gndldo pg vindcd2 *only for adjustable output version. for fixed output version, directly connect the fb pin to the output of the buck converter. 1f c 2 1f c 10 10f c 7 1f c 6 1f c 5 4.7f c 4 4.7f caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2010, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. august 15, 2011 fn7605.1
isl9305 2 fn7605.1 august 15, 2011 block diagram table 1. typical application part list parts description manufacturer part number specifications size l1, l2 inductor sumida cdrh2d14np-1r5 1.5h/1.80a/50m 3.0mmx3.0mmx1.55mm c1 input capacitor murata grm21br60j106ke19l 10f/6.3v 0805 c2, c3 input capacitor murata grm185r60j105ke26d 1f/6.3v 0603 c4, c5 output capacitor murata grm219r60j475ke01d 4.7f/6.3v 0805 c6, c7 output capacitor murata grm185r60j105ke26d 1f/6.3v 0603 r1, r2, r3, r4 resistor various 1%, smd, 0.1 0603 note: 1. c4 and c5 are 10f/6.3v for vodcd less than 1v. ldo1 300ma i 2 c interface dcd2 buck converter uvlo vref osc vindcd1 fb1 sw1 gnddcd1 vindcd2 fb2 sw2 gnddcd2 vinldo1 voldo1 vinldo2 voldo2 sdat sclk dcdpg gndldo 10f 10f 1f 10f 4.7f 4.7f 10f 1f 1.5h 1.5h dcd1 buck converter overcurrent protection analog/logic circuit input thermal shutdown pgood with 1~200ms delay time ldo2 300ma short circuit protection
isl9305 3 fn7605.1 august 15, 2011 pin configuration isl9305 (16 ld 4x4 tqfn) top view e-pad 1 2 3 4 5678 9 10 11 12 13 14 15 16 gnddcd2 sclk gndcdc1 vindcd1 sw1 dcdpg sw2 fb2 vindcd2 fb1 sdat vinldo1 voldo1 gndldo vinldo2 voldo2 pin descriptions pin number (tqfn) name description 1 vindcd1 input voltage for buck converter dcd1 and it also serves as the power supply pin for th e whole internal digital/ analog circuits. 2 fb1 feedback pin for dcd1, connect external voltage divider resistors between dcdc1 output, this pin and ground. for fixed output versions, connect this pin directly to the dcd1 output. 3sclki 2 c interface clock pin. 4sdati 2 c interface data pin. 5 vinldo1 input voltage for ldo1. 6 voldo1 output voltage of ldo1. 7 voldo2 output voltage of ldo2. 8 vinldo2 input voltage for ldo2. 9 gndldo power ground for ldo1 and ldo2. 10 dcdpg the dcdpg pin is an open-drain output to indicate the state of the dcd1/dcd2 output voltages. when both dcd1 and dcd2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter voltages are within the power-good range. the pin will be pu lled low if either dcd is outside their range. when only one dcd is enabled, the state of the enabled dcd?s output will define the state of the dcdpg pin. the dcdpg state can be programmed for a delay of up to 200ms before being released to rise high. the programming range is 1ms~200ms through the i 2 c interface. 11 fb2 feedback pin for dcd2, connect external voltage divider resistors between dcd2 output, this pin and ground. for fixed output versions, connect this pin directly to the dcd2 output. 12 vindcd2 input voltage for buck converter dcd2. 13 sw2 switching node for dcd2, connect to one terminal of the inductor. 14 gnddcd2 power ground for dcd2. 15 gnddcd1 power ground for dcd1. 16 sw1 switching node for dcd1, connect to one terminal of the inductor. e-pad e-pad exposed pad. connect to system ground.
isl9305 4 fn7605.1 august 15, 2011 ordering information part number (notes 1, 2, 3) part marking fbsel dcd1 (v) fbsel dcd2 (v) slv ldo1 (v) slv ldo2 (v) temp. range (c) package tape and reel (pb-free) pkg. dwg. # isl9305irtaanlz-t 9305i aanlz adj adj 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9305irtbcnlz-t 9305i bcnlz 1.5 1.8 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9305irtbfncz-t 9305i bfncz 1.5 2.5 3.3 1.8 -40 to +85 16 ld tqfn l16.4x4g isl9305irtwbnlz-t 9305i wbnlz 1.2 1.5 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9305irtwclbz-t 9305i wclbz 1.2 1.8 2.9 1.5 -40 to +85 16 ld tqfn l16.4x4g isl9305irtwcnlz-t 9305i wcnlz 1.2 1.8 3.3 2.9 -40 to +85 16 ld tqfn l16.4x4g isl9305irtwcnyz-t 9305i wcnyz 1.2 1.8 3.3 0.9 -40 to +85 16 ld tqfn l16.4x4g isl9305irtwlncz-t 9305i wlncz 1.2 2.9 3.3 1.8 -40 to +85 16 ld tqfn l16.4x4g isl9305irtbcnlzev1z evaluation board isl9305irtbfnczev1z evaluation board ISL9305IRTAANLZEV1Z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl9305 . for more information on msl please see techbrief tb363 .
isl9305 5 fn7605.1 august 15, 2011 absolute maximum ratings (refer to ground) thermal information sw1, sw2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5v to 6.5v fb1, fb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 3.6v gnddcd1, gnddcd2, gndldo. . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd ratings human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . .3.5kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 2.2kv charged device model (tested per jesd22-c101d) . . . . . . . . . . . 225v latch up (tested per jesd78b, class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 16 ld tqfn package (notes 4, 5) . . . . . . . 40.2 5 maximum junction temperature range . . . . . . . . . . . . . .-40c to +150c recommended junction temperature range . . . . . . . . .-40c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions vindcd1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to 5.5v vindcd2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3v to vindcd1 vinldo1 and vinldo2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5v to vindcd1 dcd1 and dcd2 output current . . . . . . . . . . . . . . . . . . . . . 0ma to 800ma ldo1 and ldo2 output current . . . . . . . . . . . . . . . . . . . . . . 0ma to 300ma operating ambient temperature . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 5. jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, all parame ter limits are guaranteed over the recommended operating conditions and the typical specifications are meas ured at the following conditions: t a = +25c, vindcd1 = 3.6v, vindcd2 = 3.3v. for ldo1 and ldo2, vinldox = voldox + 0.5v to 5.5v with vinldox always no higher than vindcd1, l 1 =l 2 = 1.5h, c 1 = 10f, c 4 = c 5 = 4.7f, c 2 = c 3 = c 6 = c 7 = 1f, i out = 0a for dcd1, dcd2, ldo1 and ldo2 (see figure 1 on page 1 for more details). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol test conditions min (note 6) typ max (note 6) unit vindcd1, vindcd 2 voltage range 2.3 - 5.5 v vindcd1, vindcd2 undervoltage lockout threshold v uvlo rising - 2.2 2.3 v falling 1.9 2.1 - v quiescent supply current on vindcd1 i vin1 only dcd1 enabled, no load and no switching on dcd1 -40 60 a i vin2 only dcd1 and ldo1 enab led, with no load and no switching on dcd1 -65 95 a i vin3 both dcd1 and dcd2 enabled, no load and no switching on both dcd1 and dcd2 -50 75 a i vin4 only ldo1 and ldo2 enabled - 75 100 a i vin5 dcd1, dcd2, ldo1 and ldo2 are enabled, with no load and no switching on both dcd1 and dcd2 -100 130 a i vin6 only one dcd in forced pwm mode, no load - 4 7.5 ma shutdown supply current i sd vindcd1 = 5.5v, dcd1, dcd2, ldo1 and ldo2 are disabled through i 2 c interface, vindcd1 = 4.2v -0.15 5 a thermal shutdown - 155 - c thermal shutdown hysteresis -30- c dcd1 and dcd2 fb1, fb2 regulation voltage v fb 0.785 0.8 0.815 v fb1, fb2 bias current i fb fb = 0.75v - 0.001 - a output voltage accuracy v in = v o + 0.5v to 5.5v (minimal 2.3v), 1ma load -3 - +3 % line regulation v in = v o + 0.5v to 5.5v (minimal 2.3v) - 0.1 - %/v
isl9305 6 fn7605.1 august 15, 2011 maximum output current 800 --ma p-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.14 0.2 ? v in = 2.3v, i o = 200ma - 0.24 0.40 ? n-channel mosfet on-resistance v in = 3.6v, i o = 200ma - 0.11 0.2 ? v in = 2.3v, i o = 200ma - 0.18 0.34 ? p-channel mosfet peak current limit i pk 1.075 1.3 1.6 a sw maximum duty cycle - 100 - % sw leakage current v in = 5.5v - 0.005 1 a pwm switching frequency f s 2.6 3.0 3.4 mhz sw minimum on-time vfb = 0.75v - 70 - ns bleeding resistor - 115 - ? pg output low voltage sinking 1ma, fb1 = fb2 = 0.7v - - 0.25 v rising delay time based on 1ms programmed nominal delay time 0.6 1.1 1.8 ms falling delay time based on 1ms programmed nonimal delay time -30-s pg pin leakage current pg = vindcd1 = vindcd2 = 3.6v - 0.005 0.1 a pg low rising threshold percentage of nominal regulation voltage - 91 - % pg low falling threshold percentage of nominal regulation voltage - 87 - % pg high rising threshold percentage of nominal regulation voltage - 112 - % pg high falling threshold percentage of nominal regulation voltage - 109 - % ldo1 and ldo2 vinldo1, vinldo2 supply voltage no higher than vindcd1 1.5 - 5.5 v vinldo1, vinldo2 undervoltage lock-out threshold v uvlo vindcd1 = 2.3v, rising - 1.41 1.46 v vindcd1 = 2.3v, falling 1.33 1.37 - v internal peak current limit 350 425 540 ma dropout voltage i o = 300ma, vo 2.1v - 125 250 mv i o = 300ma, 2.1v < vo 2.8v - 100 200 mv i o = 300ma, vo > 2.8v - 80 170 mv power supply rejection ratio i o = 300ma @ 1khz, v in = 3.6v, vo = 2.6v, t a = +25c -55-db output voltage noise v in = 4.2v, i o = 10ma, t a = +25c, bw = 10hz to 100khz -45-v rms note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications unless otherwise noted, all parame ter limits are guaranteed over the recommended operating conditions and the typical specifications are meas ured at the following conditions: t a = +25c, vindcd1 = 3.6v, vindcd2 = 3.3v. for ldo1 and ldo2, vinldox = voldox + 0.5v to 5.5v with vinldox always no higher than vindcd1, l 1 =l 2 = 1.5h, c 1 = 10f, c 4 = c 5 = 4.7f, c 2 = c 3 = c 6 = c 7 = 1f, i out = 0a for dcd1, dcd2, ldo1 and ldo2 (see figure 1 on page 1 for more details). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min (note 6) typ max (note 6) unit
isl9305 7 fn7605.1 august 15, 2011 theory of operation dcd1 and dcd2 introduction both the dcd1 and dcd2 conv erters on isl9305 use the peak-current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting. both converters are able to supply up to 800ma load current. the default output voltage ranges from 0.8v to 3.6v depending on the factory pre-set configuration and can be programmed via the i 2 c interface in the range of 0.825v to 3.6v at 25mv/step with a programmable slew rate. an open-drain dcdpg (dcd power-good) signal is also provided to mo nitor the dcd1 and dcd2 output voltages. optionally, both dcd1 and dcd2 can be programmed to be actively discharged via an on-chip bleeding resistor (typical 115 ? ) when the converter is disabled. skip mode (pfm mode) for dcd1/dcd2 under light load condition, the dcd1 and dcd2 can be programmed to automatically enter a pulse-skipping mode to minimize the switching loss by reducing the switching frequency. figure 2 illustrates the skip mode operation. a zero-cross sensing circuit monitors the current flowing through the sw node for zero crossing. when it is detected to cross zero for 16 consecutive cycles, the regulator enters the skip mode. during the 16 consecutive cycles, the inductor current could be negative. the counter is reset to zero when the sensed current flowing through the sw node does not cross zero during any cycle within the 16 consecutive cycles. once the converter enters the skip mode, the pulse modulation is controlled by an internal comparator while each pulse cycle remains synchronized to the pwm clock. the p-channel mosfet is turned on at the rising edge of the clock and turned off when its current reaches ~20% of the peak current limit. as the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle-over-cycle. when the output voltage is sensed to reach 1.5% above its nominal voltage, the p-channel mosfet is turned off immediately and the inductor current is fully discharged to zero and stays at zero. the outp ut voltage reduces gradually due to the load current discharging the output capacitor. when the output voltage drops to the no minal voltage, the p-channel mosfet will be turned on again, repeating the previous operations. the regulator resumes normal pwm mode operation when the output voltage is sensed to dr op below 1.5% of its nominal voltage value as shown in figure 3. 16 cycles clock i l v out 0 v out_nominal 20% peak current limit 1.015*v out_nominal figure 2. skip mode operation waveforms v eamp d i l v out v csa figure 3. pwm operation waveforms
isl9305 8 fn7605.1 august 15, 2011 soft-start the soft-start reduces the in-rush cu rrent during the start-up stage. the soft-start block limits the current rising speed so that the output voltage rises in a controlled fashion. overcurrent protection the overcurrent protection for dc d1 and dcd2 is provided on isl9305 for when an overload condition occurs. when the current at p-channel mosfet is sensed to reach the current limit, the internal protection circuit is tr iggered to turn off the p-channel mosfet immediately. dcd short-circ uit protection the isl9305 provides short-circuit protection for both dcd1 and dcd2. the feedback voltage is monitored for output short-circuit protection. when the output voltage is sensed to be lower than a certain threshold, the internal circuit will change the pwm oscillator frequency to a lower frequencies in order to protect the ic from damage. the p-channel mosfet peak current limit remains active during this state. undervoltage lock-out (uvlo) an undervoltage lock-out (uvlo) circuit is provided on isl9305. the uvlo circuit block can prev ent abnormal operation in the event that the supply voltage is too low to guarantee proper operation. the uvlo on vindcd1 is set for a typical 2.2v with 100mv hysteresis. vinldo1 and vinldo2 are set for a typical 1.4v with 50mv hysteresis. when the input voltage is sensed to be lower than the uvlo threshold, the related channel is disabled. dcdpg (dcd power-good) isl9305 offers an open-drain power-good signal with programmable delay time for monitoring the converters dcd1 and dcd2 output voltages status. when both dcd1 and dcd2 are enabled and their output voltages are within the powe r-good window, an internal power-good signal is issued to tu rn off the open-drain mosfet so the dcdpg pin voltage can be externally pulled high after a programmed delay time. if either dcd1 or dcd2 output voltages or both of them are not within the power-good window, the dcdpg outputs an open-drain logic low signal after the programmed delay time. when there is only one dcd converter (either dcd1 or dcd2) is enabled, then the dcdpg only indicates the status of this active dcd converter. for example, if only dcd1 converter is enabled and dcd2 converter is disabled, when dcd1 output is within the power-good window, internal power-good signal will be issued to turn off the open-drain mosfet so the dcdpg pin voltage is externally pulled high after the programmed delay time. if output voltage of dcd1 is outside the power-good window, the dcdpg outputs an open-drain logic low signal after the programmed delay time. it is similar when only dcd2 is enabled and dcd1 is disabled. when both converters are disabled, dcdpg always outputs the open-drain logic low signal. low dropout operation both dcd1 and dcd2 converters feature the low dropout operation to maximize the battery life. when the input voltage drops to a level that the converter can no longer operate under switching regulation to mainta in the output voltage, the p-channel mosfet is completely turned on (100% duty cycle). the dropout voltage under such a condition is the product of the load current and the on-resistance of the p-channel mosfet. minimum required input voltage v in under such condition is the sum of output voltage plus the voltage drop across the inductor and the p-channel mosfet switch. active output voltage discharge for dcd1/dcd2 the isl9305 offers a feature to actively discharge the output voltage of dcd1 and dcd2 via an internal bleeding resistor (typical 115 ? ) when the channel is disabled. this feature is enabled by default, thus outputs can be disabled individually through programming the cont rol bit in dcd_parameter register. thermal shutdown the isl9305 provides built-in th ermal protection function with thermal shutdown threshold te mperature set at +155c with +25c hysteresis (typical). when the die temperature is sensed to reach +155c, the regulator is completely shut down and as the temperature is sensed to drop to +130c (typical), the device resumes normal operation starting from the soft-start. board layout recommendations the isl9305 is a high frequency switching charger and hence the pcb layout is a very important design practice to ensure a satisfactory performance. the power loop is composed of the output inductor l, the output capacitor c out , the sw pin and the pgnd pin. it is important to make the power loop as small as possible and the connecting traces among them should be di rect, short and wide; the same practice should be applied to the connection of the vin pin, the input capacitor c in and pgnd. the switching node of the converter, the sw pin, and the traces connected to this node are very noisy, so keep the voltage feedback trace and other noise sensitive traces away from these noisy traces. the input capacitor should be placed as close as possible to the vin pin. the ground of the input and output capacitors should be connected as close as possible as well. in addition, a solid ground plane is helpful for a good emi performance. the isl9305 employs a thermal enhanced tqfn package with an exposed pad. the exposed pad sh ould be properly soldered on thermal pad of the board in order to remove heat from the ic. the thermal pad should be big enough for 9 vias as shown in figure 4.
isl9305 9 fn7605.1 august 15, 2011 i 2 c compatible interface the isl9305 offers an i 2 c compatible interface, using two pins: sclk for the serial clock and sdat for serial data respectively. according to the i 2 c specifications, a pull-up resistor is needed for the clock and data signals to connect to a positive supply. when the isl9305 and the host use different supply voltages, the pull-up resistors should be connected to the higher voltage rail. signal timing specifications should satisfy the standard i 2 c bus specification. the maximum bit ra te is 400kb/s and more details regarding the i 2 c specifications can be found from philips. i 2 c slave address the isl9305 serves as a slave device and the 7-bit default chip address is 1101000, as shown in figure 5 according to the i 2 c specifications, here the value of bit 0 determines the direction of the message (?0? means ?write? and ?1? means ?read?). i 2 c protocol figures 6, 7, and 8 show three typical i 2 c-bus transaction protocols. figure 4. exposed thermal pad 1 r/w 1 0 1 0 0 0 bit 2 bit 3 bit 0 bit 1 bit 6 bit 7 bit 4 bit 5 msb lsb figure 5. i 2 c slave address s 0 a p slave address register address data byte 1 r/w auto increment register address data byte n auto increment register address data byte 2 auto increment register address a system host isl9305 a ? acknowledge n ? not acknowledge s ? start p ? stop a a a optional figure 6. i 2 c write s 0 a p a slave address register address data byte 1 r/w auto increment register address s 1 slave address r/w n data byte n auto increment register address a data byte 2 auto increment register address a a system host isl9305 a ? acknowledge n ? not acknowledge s ? start p ? stop optional figure 7. i 2 c read specifying register address
isl9305 10 fn7605.1 august 15, 2011 i 2 c control registers all the registers are reset at initial start-up. dcd output voltage control register dcd1out, address 0x00h; dcd2out, address 0x01h s 1 a p a slave address data byte 1 r/w auto increment register address n data byte n auto increment register address a data byte 2 auto increment register address system host isl9305 a ? acknowledge n ? not acknowledge s ? start p ? stop optional figure 8. i 2 c read not specifying register address table 2. buck converters outp ut voltage control register bit name access reset description b7 reserve - 0 refer to table 3 b6 dcdxout-6 r/w 0 b5 dcdxout-5 r/w 0 b4 dcdxout-4 r/w 1 b3 dcdxout-3 r/w 0 refer to table 3 b2 dcdxout-2 r/w 0 b1 dcdxout-1 r/w 0 b0 dcdxout-0 r/w 0
isl9305 11 fn7605.1 august 15, 2011 ldo1 and ldo2 output voltage control registers ldo1out, address 0x02h and ldo2out, address 0x03h. table 3. dcd1 and dcd2 output voltage setting dcdout <7:0> dcd output voltage (v) dcdout <7:0> dcd output voltage (v) dcdout <7:0> dcd output voltage (v) dcdout <7:0> dcd output voltage (v) 00 0.825 20 1.625 40 2.425 60 3.225 01 0.850 21 1.650 41 2.450 61 3.250 02 0.875 22 1.675 42 2.475 62 3.275 03 0.900 23 1.700 43 2.500 63 3.300 04 0.925 24 1.725 44 2.525 64 3.325 05 0.950 25 1.750 45 2.550 65 3.350 06 0.975 26 1.775 46 2.575663.375 07 1.000 27 1.800 47 2.600 67 3.400 08 1.025 28 1.825 48 2.625 68 3.425 09 1.050 29 1.850 49 2.650 69 3.450 0a 1.075 2a 1.875 4a 2.675 6a 3.475 0b 1.100 2b 1.900 4b 2.700 6b 3.500 0c 1.125 2c 1.925 4c 2.725 6c 3.525 0d 1.150 2d 1.950 4d 2.750 6d 3.550 0e 1.175 2e 1.975 4e 2.775 6e 3.575 0f 1.200 2f 2.000 4f 2.800 6f 3.600 10 1.225 30 2.025 50 2.825 11 1.250 31 2.050 51 2.850 12 1.275 32 2.075 52 2.875 13 1.300 33 2.100 53 2.900 14 1.325 34 2.125 54 2.925 15 1.350 35 2.150 55 2.950 16 1.375 36 2.175 56 2.975 17 1.400 37 2.200 57 3.000 18 1.425 38 2.225 58 3.025 19 1.450 39 2.250 59 3.050 1a 1.475 3a 2.275 5a 3.075 1b 1.500 3b 2.300 5b 3.100 1c 1.525 3c 2.325 5c 3.125 1d 1.550 3d 2.350 5d 3.150 1e 1.575 3e 2.375 5e 3.175 1f 1.600 3f 2.400 5f 3.200 table 4. ldox output voltage control registers bit name access reset description b7 reserve - 0 refer to table 5 for output voltage settings b6 reserve - 0 b5 ldoxout-5 r/w 0 b4 ldoxout-4 r/w 0 b3 ldoxout-3 r/w 1 b2 ldoxout-2 r/w 1 b1 ldoxout-1 r/w 0 b0 ldoxout-0 r/w 0
isl9305 12 fn7605.1 august 15, 2011 dcd1 and dcd2 control register dcd_parameter, address 0x04h system control register sys_parameter, address 0x05h table 5. ldox output voltage settings ldoout <7:0> ldo output voltage (v) ldoout <7:0> ldo output voltage (v) ldoout <7:0> ldo output voltage (v) ldoout <7:0> ldo output voltage (v) 00 0.90 10 1.70 20 2.50 30 3.30 01 0.95 11 1.75 21 2.55 31 3.35 02 1.00 12 1.80 22 2.60 32 3.40 03 1.05 13 1.85 23 2.65 33 3.45 04 1.10 14 1.90 24 2.70 34 3.50 05 1.15 15 1.95 25 2.75 35 3.55 06 1.20 16 2.00 26 2.80 36 3.60 07 1.25 17 2.05 27 2.85 08 1.30 18 2.10 28 2.90 09 1.35 19 2.15 29 2.95 0a 1.40 1a 2.20 2a 3.00 0b 1.45 1b 2.25 2b 3.05 0c 1.50 1c 2.30 2c 3.10 0d 1.55 1d 2.35 2d 3.15 0e 1.60 1e 2.40 2e 3.20 0f 1.65 1f 2.45 2f 3.25 table 6. dcd_parameter register bit name access reset description b7 - - 0 reserved b6 dcd_phase r/w 0 dcd1 and dcd2 pwm switch selection. 0-in phase; 1 to 180 out-of-phase. b5 dcd2_ultra r/w 0 ultrasonic feature under pfm mode for dcd2. 0-disabled; 1-enabled. b4 dcd1_ultra r/w 0 ultrasonic feature under pfm mode for dcd1. 0-disabled; 1-enabled. b3 dcd2_bld r/w 1 selection of dcd2 for active output voltage discharge when disabled. 0-disabled; 1- enabled. b2 dcd1_bld r/w 1 selection of dcd1 for active output voltage discharge when disabled. 0-disabled; 1- enabled. b1 dcd2_mode r/w 1 selection on dcd2 of auto pfm/pwm mode (= 1) or forced pw mode (= 0). b0 dcd1_mode r/w 1 selection on dcd1 of auto pfm/pwm mode (= 1) or forced pw mode (= 0). table 7. sys_parameter register bit name access reset description b7 - - 0 reserved b6 i 2 c_en r/w 0 i 2 c function enable. 0-disabled; 1-enabled b5 dcdpor_1 r/w 1 dcdpor delay time setting, dcdpor[1:0]: 00 to 1ms 01 to 50ms 10 to 150ms 11 to 200m b4 dcdpor_0 r/w 0 b3 ldo2_en r/w 1 ldo2 enable selection. 0-disable, 1-enable. b2 ldo1_en r/w 1 ldo1 enable selection. 0-disable, 1-enable b1 dcd2_en r/w 1 dcd2 enable selection. 0-disable, 1-enable. b0 dcd1_en r/w 1 dcd2 enable selection. 0-disable, 1-enable
isl9305 13 fn7605.1 august 15, 2011 dcd output voltage slew rate control register dcd_srctl, address 0x06h table 8. bit name access reset description b7 dcd2sr_2 r/w 0 dcd2 slew rate setting, dcd2sr[2:0]: 000 to 0.225mv/s 001 to 0.45mv/s 010 to 0.90mv/s 011 to 1.8mv/s 100 to 3.6mv/s 101 to 7.2mv/s 110 to 14.4mv/s 111 reserved for system use (note 7) b6 dcd2sr_1 r/w 0 b5 dcd2sr_0 r/w 1 b4 reserve - 0 reserved b3 dcd1sr_2 r/w 0 dcd1 slew rate setting, dcd1sr[2:0]: 000 to 0.225mv/s 001 to 0.45mv/s 010 to 0.90mv/s 011 to 1.8mv/s 100 to 3.6mv/s 101 to 7.2mv/s 110 to 14.4mv/s 111 reserved for system use (note 7) b2 dcd1sr_1 r/w 0 b1 dcd1sr_0 r/w 1 b0 reserve - 0 reserved note: 7. the ic can be damaged when output is programmed from high to low and the slew rate register is set to 111. typical operating conditions figure 9. dcd output voltage ripple (v in = 4.2v, full load at dcd1 and dcd2) figure 10. dcd output voltage ripple (v in = 4.2v, pfm mode) sw2(5v/div) sw1(5v/div) vodcd2(20mv/div, ac-coupling) vodcd1(20mv/div, ac-coupling) il1 (500ma/div) il2 (500ma/div) vodcd2(20mv/div, ac-coupling) vodcd1(20mv/div, ac-coupling)
isl9305 14 fn7605.1 august 15, 2011 figure 11. dcd output transient response (v in =4.2v, load step: 80ma to 800ma) figure 12. ldo output transient response (v in =4.2v, step load: 30ma to 300ma) figure 13. start-up sequency (v in = 4.2v, no load) figure 14. dcd1 and dcd2 switching waveform (v in = 5v, full load on two channels) figure 15. dcd output voltage vs load (v out = 1.8v, pfm/pwm) figure 16. dcd output voltage vs load (v out = 1.2v, pfm/pwm) typical operating conditions (continued) vodcd1 (100mv/div iout_vodcd1 (500ma/div vodcd2 (10mv/div) iout_ldo1 (200ma/div voldo1 (100mv/div voldo2 (10mv/div) vodcd2 (1v/div) voldo2 (2v/div) vodcd1 (2v/div) voldo1 (1v/div) il1 (200ma/div) il2 (200ma/div) sw1 (5v/div) sw2 (5v/div) 1.76 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1 10 100 1000 10000 output current (ma) output voltage (v) v in = 3.6v v in = 5.5v v in = 2.8v 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1 10 100 1000 10000 output current (ma) output voltage (v) v in = 5.5v v in = 2.8v v in = 3.6v
isl9305 15 fn7605.1 august 15, 2011 figure 17. efficiency vs output current (v out =1.8v, forced pwm mode) figure 18. efficiency vs output current (v out =1.8v, pfm to pwm) figure 19. ripple rejection ratio vs frequency figure 20. quiescent current vs input voltage typical operating conditions (continued) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1k output current (ma) v in = 3.6v v in = 5.5v v in = 2.8v efficiency (%) 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1k output current (ma) v in = 3.6v v in = 5.5v v in = 2.8v efficiency (%) 0 10 20 30 40 50 60 70 0.1 1 10 100 1000 frequency (khz) ripple rejection ratio (db) v in = 3.6v v out = 2.6v load = 300ma psrr 40 42 44 46 48 50 52 54 56 58 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input voltage (v) v o = 1.2v dcd1 = dcd2 = no switching, no load ldo1 = ldo2 = disabled quiescent current (a) +85c -40c +25c
isl9305 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7605.1 august 15, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl9305 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 5/25/11 fn7605.1 -table 8 on page 13 changed 111 description from ?to immediate? to ?reserved for system use (note 7).? added note to table 8, which reads "the ic can be damaged when output is programmed from high to low and the slew rate register is set to 111." -changed ordering information eval board name from isl9305irtzeval1z to three separate ones isl9305irtbcnlzev1z isl9305irtbfnczev1z ISL9305IRTAANLZEV1Z -corrected theta ja thermal information on page 5 for tqfn from 42 to 40.2 -?electrical specifications? on page 5: added "boldface limits apply over th e operating temperature range, -40c to +85c." to common conditions. bolded applicable specs. changed ?compliance to datasheet limits is assured by on e or more methods: production test, characterization and/or design.? note in electrical spec table on page 6 to ?parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperatur e limits established by characterization and are not production tested.? per product line decision. -changed text under figure 15, from "vout=1.2v" to "vout=1.8v." 11/8/10 fn7605.0 initial release
isl9305 17 fn7605.1 august 15, 2011 package outline drawing l16.4x4g 16 lead thin quad flat no-lead plastic package rev 0, 4/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo220k. 7. 2 . 10 0 . 10 see detail "x" 0.30 0.05 base plane pin #1 5 8 ( 3 . 6 typ ) ( 2 . 10 ) ( 12x 0 . 65 ) ( 16x 0 . 30 ) ( 16 x 0 . 70 ) 0.75 0 . 2 ref 0 . 00 min. 0 . 05 max. c 5 4 0.10 c m index area (4x) 0.15 pin 1 6 4.00 12 4.00 9 a b 4 0.65 12x 13 4x 1.95 16 1 6 0.08 c c seating plane 0.10 c a b 16x 0 . 50 0 . 1 index area

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